Affiliation: EPFL, Switzerland
Email: giovanni.demicheli@epfl.ch
Website: si2.epfl.ch/~demichel/
Giovanni De Micheli is a research scientist in electronics and computer science. He is credited for the invention of the Network on Chip design automation paradigm and for the creation of algorithms and design tools for Electronic Design Automation (EDA). He is Professor and Director of the Integrated Systems Laboratory and Scientific Director of the EcoCloud center at EPFL Lausanne, Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He was Director of the Electrical Engineering Institute at EPFL from 2008 to 2019 and program leader of the Swiss Federal Nano-Tera.ch program. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
TO BE ANNOUNCED
TO BE ANNOUNCED
Affiliation: University of Michigan, USA
Email: valeria@umich.edu
Website: web.eecs.umich.edu/~valeria/
Valeria Bertacco is the Mary Lou Dorf Collegiate Professor of Computer Science and Engineering, and Arthur F. Thurnau Professor of Engineering at the University of Michigan. Her research interests are in the area of computer system design. Throughout her career, she has contributed novel solutions in design validation and reliability, hardware-security assurance, and the design of specialized architectures for graph algorithms and machine learning. From 2018 to 2023, Prof. Bertacco was the Director of the Applications Driving Architectures (ADA) Research Center, funded by a consortium of semiconductor companies and the Defense Advanced Research Projects Agency (DARPA). The Center engaged the work of 10 US academic institutions and over 130 Ph.D. student researchers. Currently, she leads the MAVERIC collaborative, the University of Michigan's initiative to advance semiconductor research and education. At Michigan, she also serves as the Vice Provost for Engaged Learning, supporting all international partnerships and co-curricular engagements. In the international space, her initiatives have included promoting collaborations with African institutions, through initiatives like Africa Week, UMAPS and AURA. Domestically, the primary partners reside within the State of Michigan, and especially within the City of Detroit. In her Vice Provost role, Prof. Bertacco facilitates the work of nine central units, whose goals range from promoting environmental sustainability to supporting journalists, to promoting the arts in research universities, and to increasing the participation of gender minorities in STEM fields. She received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. Prof. Bertacco joined the University of Michigan in 2003, after working as a research engineer for Systems Science Inc., and Synopsys from 1997 to 2001.
TO BE ANNOUNCED
TO BE ANNOUNCED
Affiliation: Hebrew University of Jerusalem, Israel
Email: freddy.gabbay@mail.huji.ac.il
Website: freddygabbay.huji.ac.il
Freddy Gabbay is a Professor and head of the VLSI Systems Lab at the Institute of Applied Physics at the Hebrew University of Jerusalem. His research interests span VLSI design, microelectronics, computer architecture, machine learning, and domain-specific accelerators. Throughout his career, Prof. Gabbay has contributed to the design and development of advanced semiconductor systems, combining architectural innovation with practical implementation in high-performance computing and communication devices. Prof. Gabbay’s professional experience bridges academia and industry, with over two decades of leadership in both domains. He began his career in 1998 as a researcher at Intel’s Microprocessor Research Lab. He then joined Mellanox Technologies, where he played a key role in the architecture and ASIC design of high-performance switching products. In 2003, he moved to Freescale Semiconductor as a senior design manager, leading the development of baseband ASIC solutions. He later returned to Mellanox Technologies (now part of NVIDIA) in 2012, where he served as Vice President of Chip Design, overseeing large-scale silicon development programs. In addition to his industrial leadership, Prof. Gabbay is actively engaged in the academic and professional community. He serves as an Associate Editor for IEEE Computer Architecture Letters and as Chairman of the IEEE Computer Society Israel Chapter. He holds 19 patents and is a Senior Member of IEEE. Prof. Gabbay received his B.Sc., M.Sc., and Ph.D. degrees in Electrical Engineering from the Technion - Israel Institute of Technology.
Do We Really Need All the Bits? Value-Driven Approximate Computing for AI Accelerators
Generative AI is reshaping computing, enabling breakthroughs across language, vision, and autonomous systems. However, these models come at a steep cost: they are increasingly limited by compute, memory bandwidth, and energy, pushing modern hardware systems toward fundamental scalability barriers. This keynote presents a value-driven perspective on approximate computing, leveraging the inherent resiliency of deep neural networks to rethink how AI systems are designed. Instead of treating all data uniformly, we prioritize computation and data movement based on their contribution to model accuracy. This enables aggressive optimizations through quantization, decomposition, dynamic approximation, and compression. We will showcase a set of hardware–software co-designed techniques that significantly reduce memory traffic, improve arithmetic intensity, and enhance overall system efficiency. Through case studies, we demonstrate substantial gains in performance, energy efficiency, and memory utilization, while maintaining high model accuracy. Finally, we discuss how value-driven approximate computing reshapes the design space of next-generation AI accelerators, highlighting the central role of co-design in overcoming the memory and energy bottlenecks of large-scale generative AI systems.
Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechniquede Grenoble (INPG - France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He got his PhD on Electronics in 2021 from University of Bordeaux. He is currently R&D Executive Director and General Manager of Synopsys Chile. He has published several papers in IoT, EDA, Smart Agriculture, Climate Change, and embedded systems development. From 2012 to 2024 he was chair of the IEEE Chilean join chapter EDS/CASS/SSCS. He has been part of several conferences TCP (ISCAS, ICECS, LASCAS, VLSI SoC) and Steering Committees. He was member of the IEEE CASS Board of Governors for the period 2021 - 2023. He founded the Electronics for Agrifood SIG at CASS and chaired it until 2024. He was Chair of LASCAS Steering Committee from 2018 to2022. He was CASS representative at the IEEE Climate Change TAB. He is member of the IEEE CASS Board of Governors for the period 2025 - 2027.He was President of the Chilean Electronic and Electrical Industry Association (AIE) from 2017 to 2021.From 2006 to 2008 he was member of the “Chilean Offshoring Committee” organized by the Minister of Economy of Chile. In 2010 he was awarded as “Innovator of the Year in Services Export”. In 2022 he was awarded as “IEEE/AIE Best Engineer” in Chile. In 2023 he was awarded as IEEE R9 Outstanding Engineer”. In 2024 he was awarded as “2024 CASS Meritorious Service Award”. Victor's research areas are EDA (Electronic Design Automation), Climate Change, and IoT for Smart Agriculture.
Low Power IC Design for a Sustainable World
In an era where sustainability is essential, designing low-power integrated circuits (ICs) plays a crucial role in reducing energy consumption and mitigating environmental impact. This talk examines innovative strategies in low-power IC design to meet the increasing demand for energy-efficient electronics, from IoT devices to large-scale computing systems. By utilizing advanced techniques such as subthreshold operation, power gating, clock gating, and dynamic voltage scaling, we outline a framework for optimizing performance while minimizing power dissipation. The discussion emphasizes the interplay between circuit-level innovations, such as the strategic use of clock gating to reduce dynamic power in idle states, process technology advancements, and system-level integration, highlighting their collective contribution to sustainability. Through simulations and case studies, we demonstrate how these approaches can significantly lower the carbon footprint of electronic systems, paving the way for greener technology solutions that align with global sustainability goals.
Below is the schedule for the VLSI-SoC 2026 Conference Program.
| Time | Event |
|---|---|
| 08:00 – 09:00 | Registration |
| 09:00 – 12:00 | Morning Tutorials |
| 12:00 – 13:00 | Lunch Break |
| 13:00 – 16:00 | Afternoon Tutorials |
| 16:30 – 17:30 | Welcome Reception |
| Time | Event |
|---|---|
| 08:00 – 09:00 | Registration |
| 09:00 – 10:00 | Keynote Speech 1 |
| 10:30 – 12:30 | Session 1 |
| 12:30 – 13:30 | Lunch Break |
| 13:30 – 15:30 | Session 2 |
| 16:00 – 17:00 | Panel Discussion |
| Time | Event |
|---|---|
| 08:00 – 09:00 | Registration |
| 09:00 – 10:00 | Keynote Speech 2 |
| 10:30 – 12:30 | Session 3 |
| 12:30 – 13:30 | Lunch Break |
| 13:30 – 15:30 | Session 4 |
| 16:00 – 17:00 | Panel Discussion |
| Time | Event |
|---|---|
| 08:00 – 09:00 | Registration |
| 09:00 – 10:00 | Keynote Speech 3 |
| 10:30 – 12:30 | Session 5 |
| 12:30 – 13:30 | Lunch Break |
| 13:30 – 15:30 | Conference conclusion |
Below you can view or download the Program Flyer and Detailed Program files.
Info will be posted. (TBA)
