Keynote Title

Sustainable and Secure Computing: the Last Frontier

Abstract

This keynote explores the convergence of sustainability and security in modern computing, highlighting key challenges and emerging approaches for building energy-efficient and resilient systems.

Keynote Title

Envisioning SoC Design with an Army of Agentic Minions.

Abstract

Keynote Title

Do We Really Need All the Bits? Value-Driven Approximate Computing for AI Accelerators

Abstract

Generative AI is reshaping computing, enabling breakthroughs across language, vision, and autonomous systems. However, these models come at a steep cost: they are increasingly limited by compute, memory bandwidth, and energy, pushing modern hardware systems toward fundamental scalability barriers. This keynote presents a value-driven perspective on approximate computing, leveraging the inherent resiliency of deep neural networks to rethink how AI systems are designed. Instead of treating all data uniformly, we prioritize computation and data movement based on their contribution to model accuracy. This enables aggressive optimizations through quantization, decomposition, dynamic approximation, and compression. We will showcase a set of hardware–software co-designed techniques that significantly reduce memory traffic, improve arithmetic intensity, and enhance overall system efficiency. Through case studies, we demonstrate substantial gains in performance, energy efficiency, and memory utilization, while maintaining high model accuracy. Finally, we discuss how value-driven approximate computing reshapes the design space of next-generation AI accelerators, highlighting the central role of co-design in overcoming the memory and energy bottlenecks of large-scale generative AI systems.

Keynote Title

Low Power IC Design for a Sustainable World

Abstract

In an era where sustainability is essential, designing low-power integrated circuits (ICs) plays a crucial role in reducing energy consumption and mitigating environmental impact. This talk examines innovative strategies in low-power IC design to meet the increasing demand for energy-efficient electronics, from IoT devices to large-scale computing systems. By utilizing advanced techniques such as subthreshold operation, power gating, clock gating, and dynamic voltage scaling, we outline a framework for optimizing performance while minimizing power dissipation. The discussion emphasizes the interplay between circuit-level innovations, such as the strategic use of clock gating to reduce dynamic power in idle states, process technology advancements, and system-level integration, highlighting their collective contribution to sustainability. Through simulations and case studies, we demonstrate how these approaches can significantly lower the carbon footprint of electronic systems, paving the way for greener technology solutions that align with global sustainability goals.

Keynote Title

Bridging the gap between research and industry through embedded systems

Abstract

This keynote explores how embedded systems enable the translation of research innovations into real-world industrial applications, highlighting challenges and strategies for effective technology transfer.

Keynote Title

What is the IP Reuse Trap for Digital Hardware, and how can it be escaped?

Abstract

Despite its theoretical high productivity impact, IP reuse (intellectual property reuse) in semiconductor design—the practice of using pre-designed digital hardware blocks (like processor cores, interface components, …) in new System-on-a-Chip (SoC) projects—frequently fails to work as expected in industry due to several causes:
- High integration complexity, including reading and understanding (often incomplete) documentation, physical dependencies between IP and environment, and finding the right configuration
- The IP only mostly fits, but changes in the IP are needed due to lacking features, adaptation to meet different PPA constraints, and to use the IP in different technologies.
- IP development is costly and takes more time for development than non-reusable components.
Reasons are manifold:
- Interfaces even to widely used buses like AHB allow many variations, resulting in a very high space of options.
- RTL synthesis capabilities are limited; QoS—quality of source—is still the dominating principle. Different PPA constraints require re-architecting and re-implementing to satisfy them.
- Also, different power-down, security, and safety constraints require modifying IPs.
- Lastly, a verified IP must be verified and, more importantly, validated in its environment: Does the IP provide the intended functionality to the overall system?
The talk addresses these challenges from semiconductor industry's point of view. It first introduces these and some other challenges. An elaboration of methods dealing with the challenges, such as platform-based design, IP generation as well as hardware generation languages, and automated interface adoption, follows. It closes with the discussion of whether we are reusing the right things and in the right way.

Title

AI as the Chip Designer: Evolution or Illusion?

Abstract

Artificial intelligence is entering System-on-Chip design at every level, from automating repetitive engineering tasks to supporting architectural exploration, optimization, and verification. This panel will discuss whether AI can deliver meaningful productivity gains and open new design possibilities, or whether it also risks weakening engineering expertise, trust, and accountability. Bringing together perspectives from academia, startups, and industry, the discussion will ask whether AI marks a true paradigm shift in SoC engineering or remains a powerful tool whose impact depends on human oversight, responsibility, and judgment.

Panelists

Prof. Christos Sotiriou, University of Thessaly

Dr. Sandro Belfanti, Chipmind

Dr. Valerio Tenace, PrimisAI

Dr. Frank K. Gurkaynak, ETH

Tutorial Title

TO BE ANNOUNCED

Speaker

TBA

Topic

TO BE ANNOUNCED